The present invention relates to direct memory access apparatus for use in a computer system and, more particularly, to novel DMA apparatus utilized with a microcomputer system for altering the contents of memory without altering the speed of central processing unit operation.
Generally, the central processing unit (CPU) of a computer system, and especially of a microcomputer system, executes each of a plurality of instructions in sequential manner. Each instruction typically requires one or more machine cycles with each machine cycle requiring several cycles of a master clock frequency, and hence a calculable time interval, for completion. Such systems may be configured to operate in a direct memory access (DMA) mode, whereby data is written into, or read from, a system memory means from a source other than the CPU; the CPU is generally halted during the DMA time interval, causing the through-put of the CPU to be drastically reduced. In at least one known microcomputer sytem, the use of the DMA mode requires that at least one complete machine cycle, consisting of several clock periods, be given up (and the CPU kept idle) to allow each direct memory access to be completed. Frequent direct memory accessing can slow the average instruction completion time by a relatively large factor. It is, therefore, desirable to provide direct memory access apparatus which does not interrupt the operation of the CPU and does not affect the average time for completion of a CPU instruction, even while allowing a direct memory access to occur at least once in each instruction cycle, and preferably at least once in each machine cycle.